1. Technical Field
This disclosure is directed to electronic circuits, and more particularly, clock divider circuits used to vary the frequency of a clock signal.
2. Description of the Related Art
Synchronous circuits implemented on an integrated circuit (IC) utilize a clock signal. Synchronous circuits such as flip-flops and other circuit types may change states responsive to an edge (e.g., a rising edge) of a received clock signal. Thus, such state changes may be controlled so that they are performed at certain times, thereby synchronizing the operation of the various circuits. This may be of particular importance in certain IC subsystems, such as data path subsystem.
In many ICs, some clock frequencies may be varied during operation for different reasons. For example, the frequency of a clock signal may be increased in order to enable higher performance (e.g., higher data throughput), or may be decreased in order to reduce power consumption. Various types of circuits may be used to accomplish frequency variation of clock signals. One such type of circuit is a clock divider. A clock divider may receive a clock signal at a first frequency and output a corresponding clock signal at a second frequency that is less than the first. For example, a clock divider may receive a clock signal having a frequency of 800 MHz, and may output a corresponding clock signal at a frequency of 400 MHz. Thus, the frequency of the input clock signal is divided by two in this example to produce the output clock signal at the reduced frequency.